/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND,
EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR PURPOSE.
++*/
/*--
Module Name:
    hwpcie950.h
Abstract:
    Type definitions and data for the pcie950 based serial port driver

Notes:
--*/

#ifndef __HW_PCIE950_H_
#define __HW_PCIE950_H_

#include "hw16950.h"

#ifdef __cplusplus
extern "C" {
#endif

//
// Offsets from the base register address of the
// various bar registers for the pcie950 family of UARTS.
//

#define MAXIMUM_NUMBER_OF_DEVICES 4
#define MAXIMUM_NUMBER_OF_PORTS   16

typedef struct
{
    union
    {
        UCHAR ucTransmitHoldingReg;
        UCHAR ucReceiveHoldingReg;
    };
    UCHAR ucInterruptEnableReg;
    union
    {
        UCHAR ucInterruptStatusReg;
        UCHAR ucFifoControlReg;
    };
    UCHAR ucLineControlReg;
    UCHAR ucModemControlReg;
    UCHAR ucLineStatusReg;
    UCHAR ucModemStatusReg;
    UCHAR ucScratchReg;
    UCHAR rsv0[0x78];
    union
    {
        DWORD dwRhrReg;
        DWORD dwThrReg;
        WORD  wRhrReg;
        WORD  wThrReg;
        BYTE  ucRhrReg;
        BYTE  ucThrReg;
    };
    union
    {
        DWORD dwTflRflIsrLsrReg;
        struct
        {
            WORD wIsrLsrReg;
            WORD wTflRflReg;
        };
        struct
        {
            BYTE ucLsrReg;
            BYTE ucIsrReg;
            BYTE ucRflReg;
            BYTE ucTflReg;
        };
    };
    UCHAR rsv1[8];
    UCHAR rsv2[2];                  // @ 0x90
    UCHAR ucEnhancedFeaturesReg;
    UCHAR rsv3;
    UCHAR ucXOnCharactor1Reg;
    UCHAR ucXOnCharactor2Reg;
    UCHAR ucXOffCharactor1Reg;
    UCHAR ucXOffCharactor2Reg;
    UCHAR rsv4[8];
    UCHAR rsv5;                    // @ 0xA0
    UCHAR ucAdditionalStatusReg;
    UCHAR rsv6;
    UCHAR ucReceiveFifoLevelReg;
    UCHAR ucTransmitFifoLevelReg;
    UCHAR ucIndexedControlReg;
    UCHAR rsv7[2];
    UCHAR rsv8[0x18];
    UCHAR ucAdditionalControlReg;     // @ 0xC0
    UCHAR ucClockPrescalerReg;
    UCHAR ucTimesControlReg;
    UCHAR ucClockPrescaler2Reg;
    UCHAR ucTransmitIntTrigLevelReg;
    UCHAR ucReceiveIntTrigLevelReg;
    UCHAR ucReceiveFlowOnLevelReg;
    UCHAR ucReceiveFlowOffLevelReg;
    UCHAR ucHardwareId1Reg;           // = 0x16
    UCHAR ucHardwareId2Reg;           // = 0xC9
    UCHAR ucHardwareId3Reg;           // = 0x50
    UCHAR ucHardwareRevisionReg;
    UCHAR ucChanneSoftResetReg;
    UCHAR ucNineBitModeReg;
    UCHAR ucModemDisableMaskReg;
    UCHAR ucReadableFcrReg;
    UCHAR ucGoodDataStatusReg;
    UCHAR ucInternalReadyReg;
    UCHAR ucPortIndexReg;
    UCHAR rsv9;
    UCHAR ucRs485ControlReg;
    UCHAR ucRs485DelayReg;
    UCHAR rsv10[2];
    UCHAR ucAltLatchReg;
    UCHAR ucAltEnablereg;
    UCHAR ucAltDivisorLatchLsbReg;
    UCHAR ucAltDivisorLatchMsbReg;
    UCHAR ucAltClockPrescalerReg;
    UCHAR ucAltTimesControlReg;
    UCHAR ucAltClockPrescaler2Reg;     // @ oxDE
    UCHAR rsv11[0x21];
    DWORD dwDmaAddressLowReg;          // @ 0x100
    DWORD dwDmaAddressHighReg;
    DWORD dwDmaTransferLengthReg;
    DWORD dwDmaStatusReg;
    UCHAR rsv12[0xF0];                 // end @ 0x1FF
} UART_REGS, *PUART_REGS;

#define ucDivisorLatchLsbReg  ucTransmitHoldingReg
#define ucDivisorLatchMsbReg  ucInterruptEnableReg

#define SHADOW_LSR_SHIFT16    0
#define SHADOW_ISR_SHIFT16    8
#define SHADOW_RFL_SHIFT16    0
#define SHADOW_TFL_SHIFT16    8
#define SHADOW_LSR_SHIFT32    0
#define SHADOW_ISR_SHIFT32    8
#define SHADOW_RFL_SHIFT32    16
#define SHADOW_TFL_SHIFT32    24

#define SHADOW_LSR_MASK16     (0xFF << SHADOW_LSR_SHIFT16)
#define SHADOW_ISR_MASK16     (0xFF << SHADOW_ISR_SHIFT16)
#define SHADOW_RFL_MASK16     (0xFF << SHADOW_RFL_SHIFT16)
#define SHADOW_TFL_MASK16     (0xFF << SHADOW_TFL_SHIFT16)
#define SHADOW_LSR_MASK32     (0xFF << SHADOW_LSR_SHIFT32)
#define SHADOW_ISR_MASK32     (0xFF << SHADOW_ISR_SHIFT32)
#define SHADOW_RFL_MASK32     (0xFF << SHADOW_RFL_SHIFT32)
#define SHADOW_TFL_MASK32     (0xFF << SHADOW_TFL_SHIFT32)

#define GetShadowLSR16(il)    (BYTE)((il   & SHADOW_LSR_MASK16) >> SHADOW_LSR_SHIFT16)
#define GetShadowISR16(il)    (BYTE)((il   & SHADOW_ISR_MASK16) >> SHADOW_ISR_SHIFT16)
#define GetShadowRFL16(tr)    (BYTE)((tr   & SHADOW_RFL_MASK16) >> SHADOW_RFL_SHIFT16)
#define GetShadowTFL16(tr)    (BYTE)((tr   & SHADOW_TFL_MASK16) >> SHADOW_TFL_SHIFT16)
#define GetShadowLSR32(tril)  (BYTE)((tril & SHADOW_LSR_MASK32) >> SHADOW_LSR_SHIFT32)
#define GetShadowISR32(tril)  (BYTE)((tril & SHADOW_ISR_MASK32) >> SHADOW_ISR_SHIFT32)
#define GetShadowRFL32(tril)  (BYTE)((tril & SHADOW_RFL_MASK32) >> SHADOW_RFL_SHIFT32)
#define GetShadowTFL32(tril)  (BYTE)((tril & SHADOW_TFL_MASK32) >> SHADOW_TFL_SHIFT32)


#define DMA_LENGTH_DIRECTION_RECEIVE (0x1 << 31)
#define DMA_LENGTH_MAXIMUM_LENGTH    128

#define DMA_STATUS_DMA_DONE          (0x1 << 2)
#define DMA_STATUS_DMA_ERROR         (0x1 << 1)
#define DMA_STATUS_DMA_ACTIVE        (0x1 << 0)

#define RS485_PHASE_DELAY_SHIFTS     0
#define RS485_PHASE_DELAY_MASK       (0xF << RS485_PHASE_DELAY_SHIFTS)
#define RS485_BIT_DELAY_SHIFTS       4
#define RS485_BIT_DELAY_MASK         (0xF << RS485_BIT_DELAY_SHIFTS)

#define RS485_DELAY_ENABLE           (0x1 << 0)
#define RS485_DELAY_DISABLE          (0x0 << 0)

typedef struct
{
    DWORD           dwClassCodeReg;
    DWORD           dwNumberOfUartsReg;
    DWORD           dwGlobalIrqStatusReg;
    DWORD           dwGlobalIrqEnableReg;
    DWORD           dwGlobalIrqDisableReg;
    DWORD           dwGlobalWakeEnableReg;
    DWORD           dwGlobalWakeDisableReg;
    DWORD           dwGlobalLoopbackControlReg;
    BYTE            rsv[0xFE0];
    UART_REGS       Uarts[16];
} PCIE950_BAR0_REGS, *PPCIE950_BAR0_REGS;

#define RECEIVE_BUFFER_32BIT_REGISTER      0x80
#define TRANSMIT_HOLDING_32BIT_REGISTER    0x80
#define RAPID_LINE_STATUS_REGISTER         0x84
#define RAPID_INTERRUPT_IDENT_REGISTER     0x85
#define RAPID_RECEIVE_FIFO_LEVEL_REGISTER  0x86
#define RAPID_TRANSMIT_FIFO_LEVEL_REGISTER 0x87
#define RAPID_TFL_RFL_ISR_LSR_REGSTERS     0x84

#define SUPPORT_LINE_DRIVER_DELAY_CONTROL  TRUE

#ifdef __cplusplus
}
#endif

#endif // __HW_PCIE950_H_

